1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and to a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits, particularly integrated circuits using MOS transistors, are increasing in integration. With increases in integration, MOS transistors used in the integrated circuits increasingly become finer up to a nano-level. Such finer MOS transistors have the problem of difficulty in suppressing leak currents and difficulty in decreasing areas occupied by circuits in view of the demand for securing necessary amounts of currents. In order to resolve the problem, there are proposed surrounding gate transistors (referred to as “SGT” hereinafter) having a structure in which a source, gate, and drain are disposed perpendicularly to a substrate, and a gate electrode surrounds a pillar-shaped semiconductor layer (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
A conventional SGT manufacturing method includes forming a silicon pillar having a pillar-shaped nitride film hard mask formed thereon, forming a diffusion layer in a lower portion of the silicon pillar, depositing a gate material, planarizing the gate material, etching back the gate material, and forming an insulating film sidewall on sidewalls of the silicon pillar and the nitride film hard mask. Then, a resist pattern for a gate line is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed in an upper portion of the silicon pillar (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-182317). Then, a nitride film sidewall is formed on the sidewall of the silicon pillar, a diffusion layer is formed in an upper portion of the silicon pillar by ion implantation, a nitride film is formed as a contact stopper, an oxide film is formed as an interlayer film, and then contact etching is performed.
Therefore, the sidewall of the upper portion of the silicon pillar is covered with a nitride film sidewall, and a contact is in contact with the upper surface of the silicon pillar. An area of contact between the contact and the upper portion of the silicon pillar decreases as the diameter of the silicon pillar decreases, thereby increasing resistance.
Also, the conventional SGT manufacturing method separately forms a contact hole on the silicon pillar and a contact hole on a planar silicon layer disposed below the silicon pillar because contacts have different depths (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-004244). The separated formation increases the number of steps.
In spite of separated formation, excessive etching of the contact hole on the silicon pillar may cause the contact hole to reach a gate electrode, while insufficient etching may cause insulation between the upper portion of the silicon pillar and the contact.
The contact hole on the planar silicon layer disposed below the silicon pillar is deep and thus hard to fill. Also, a deep contact hole is difficult to form.
Further, a thinner silicon pillar becomes difficult to introduce impurities because of a silicon density of 5×1022/cm3.
It is known that in a planar MOS transistor, a sidewall of a LDD region is composed of polycrystalline silicon of the same conductivity type as a low-concentration layer, and surface carriers of the LDD region are induced by a difference in work function, and thus the impedance of the LDD region can be decreased as compared with an oxide film sidewall LDD-type MOS transistor (for example, refer to Japanese Unexamined Patent Application Publication No. 11-297984). It is also known that the polycrystalline silicon sidewall is electrically insulated from a gate electrode. Further it is shown in a drawing that the polycrystalline silicon sidewall is insulated from source and drain through an interlayer insulating film.